Instruction cycle

Instruction cycle:

                       An instruction is command given to computer to perform a specified on given data,to perform a particular task a programmer writes a sequence of instruction called a program.Program and data are store in the memory.the microprocessor fetches one instruction from the memory a time and executes.It executes all the instruction of a program.one by one to produce the final result.

              The necessary steps that a microprocessor  carry out to an instruction and necessary data from the memory and to executes if constitute an instruction cycle.
                      A instruction cycle is composed of two cycle;one in fetch cycle and another in execute cycle.

Fetch cycle:
                    In fetch cycle,microprocessor  fetch up code from the memory the necessary steps which are carried out to fetch an up code from the memory constitute of fetch cycle.

Execute cycle:
                     The necessary step that are carried out to get data if  any from the memory and to perform the specific operation specified in an instruction constitute and execute cycle.
                              The time required to execute an instructions variable which depends on the type of instruction to be executed.The total time required to execute an instruction is given by:

                                     IC = FC+EC
                                               Where,IC=instruction cycle
                                                          FC=fetch cycle
                                                           EC=execute cycle

Fetch-execution overlap (instruction pipe lining )

Instruction processing can be divided into two stages:

1. Fetch instruction
2. Execute instruction

There are  time during the execution of instruction when main memory is not being accessed.This time could be used to fetch the next instruction in parallel with the executive of current one.Figure depicts this approach is called instruction pipe lines.
                     

figure:single processor system

fetch-execution overlap in dual processor system

                                           FIGURE:Two stage instruction pipe line

         The pipe line has two independent stages. The 1st stage fetch an instruction & buffers it. When the second stage is free,the 1st stages passes the buffered instruction,while the 2nd stages is executing the instructing ,the 1st stage takes advantages of unused memory cycle to fetch and buffer the next instruction.These is called Fetch-Execution  overlap or instruction pipeline.
these process will speed up instruction execution.if the fetch and execute stages where of equal duration the instruction cycle time will be half.

Decoder

Definition of decoder.

A decoder is a combinational circuit that converts binary information from "n" i/p lines to a maximum of 2nd unique output lines.a decoder is similar to demultiplexer with one exception that is their is no data input.the only i/p's are control bit's A,B,C as an figure below,
    Examples.
                  3 line to 8 lines decoder (3 to 8 line) or binary to octal decoder.
                              The logic circuit is called one of a decoder because only one of  8 o/p is high at a time.when A,B,C is 001 then, Y_{1  AND gate has all  i/p's and 8 o/p lines.it is also known as 3 to 8 line or binary to octal decoder.}

Truth table of 3 to 8 line Decoder:

A     B     C                               Y₀      Y₁   Y₂    Y₃    Y₄    Y₅    Y₆     Y₇

         0       0       0                              1        0      0      0     0      0      0       0
         0       0       1                               0       1      0      0     0      0      0       0
         0       1       0                               0       0      1      0     0      0      0       0
         0       1       1                               0       0      0      1     0      0      0       0
         1       0       0                               0       0      0      0     1      0      0       0
         1       0       1                               0       0      0      0     0      1      0       0
         1       1       0                               0       0      0      0     0      0      1       0
         1       1       1                               0       0      0      0     0      0      0       1




















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