Fetch-execution overlap (instruction pipe lining )

Instruction processing can be divided into two stages:

1. Fetch instruction
2. Execute instruction

There are  time during the execution of instruction when main memory is not being accessed.This time could be used to fetch the next instruction in parallel with the executive of current one.Figure depicts this approach is called instruction pipe lines.
                     

figure:single processor system

fetch-execution overlap in dual processor system

                                           FIGURE:Two stage instruction pipe line

         The pipe line has two independent stages. The 1st stage fetch an instruction & buffers it. When the second stage is free,the 1st stages passes the buffered instruction,while the 2nd stages is executing the instructing ,the 1st stage takes advantages of unused memory cycle to fetch and buffer the next instruction.These is called Fetch-Execution  overlap or instruction pipeline.
these process will speed up instruction execution.if the fetch and execute stages where of equal duration the instruction cycle time will be half.